As it is well known, technology scaling is leading to an exponential increase in integrated circuit leakage current, such that below 90 nm static power could be the dominant factor in energy consumption.
In particular, configurable structures such as FPGA (Field-Programmable Gate Arrays) architectures are affected more heavily than other devices such as ASICs by this problem, since they may require many more transistors to support their main feature, the reconfigurability.
Indeed, configurable logic structures have become a valid alternative to ASICs because of the provided software programmability which reduces the design cycle, while density and running frequency greatly increase. It is well known that this flexibility is achieved at the cost of a larger silicon area occupation to accommodate the logic blocks that realize reconfigurability.
However, as technology scales, the area constraint is becoming less restrictive, while the large number of integrated transistors in FPGA architectures is still a source of higher energy consumption of such architectures than the ASIC ones.
Since reconfigurable computing is a promising technology for wireless applications, where systems need to support a variety of changing communication protocols, the power consumption constraint is becoming the main issue that could prevent FPGA architectures from being widely used in this field.
A typical configuration of an FPGA architecture is schematically shown in FIG. 1A and globally indicated with 1. The FPGA architecture 1 comprises a plurality of programmable logic elements 2 arranged in a matrix-like configuration, commonly indicated as gate arrays, each of such programmable logic elements 2 being connected, by means of a plurality of local connections 3, to an interconnection network 4, in turn comprising a plurality of horizontal interconnection lines 4a and vertical interconnection lines 4b. 
As shown in the figure, each programmable logic element 2 of the gate array comprises one or more computational blocks 5 such as look-up tables, ALUs, etc. having a plurality of inputs and being connected to an output through a multiplexer 6 having in turn an input connected to a memory element 7.
In particular, the interconnection network 4 allows reconfiguring the FPGA architecture 1, changing the operation thereof.
FIG. 1B schematically shows a FPGA architecture 1, depicted in island-style, and comprising a switch matrix 9 of switch blocks for connecting a plurality of connection lines.
In particular, the figure shows how the programmable logic element 2 is connected to a horizontal connection block 8a and to a vertical connection block 8b in turn connected to the switch matrix 9, in turn comprising a plurality of switches 10.
When power consumption of a FPGA architecture is considered, it is immediately evident that a large part of the device area is often left completely unused when a specific circuit is mapped, and its power consumption is useless.
Several studies have been conducted on dynamic power reduction for FPGA architectures, i.e., provides no benefit.
Recent studies mainly focus on proposing solutions for the routing architecture since this is usually responsible for 60% to 80% of the power consumption, area, and delay of reconfigurable devices such as of the FPGA architectures.
Other works have addressed the problem of reducing active leakage power consumption which is a challenging task since standard techniques configuring a part of logic in sleep mode often cannot apply. This problem of reducing active leakage consumption, evaluating different Hw/Sw techniques, has been described by Anderson et al in the article entitled: “Active leakage Power Optimization for FPGA”, Proceedings of the International Symposium on FPGAS, pages 33-41. ACM, February 2004, which is incorporated by reference.
As a matter of fact, the fraction of power consumption due to leakage current in FPGA architectures is rapidly increasing as technology advances. This is mainly due to the threshold voltage scaling which leads to an exponential increase in the subthreshold leakage.
Since leakage generates static power consumption which depends on the number of integrated transistors, FPGA architectures will be suffering from this problem even more than other devices.
It can be verified that the switch block contribution is dominant, since it contains larger buffers and leakage current is proportional to transistor width. Therefore, in order to reduce the overall leakage power consumption, a new circuit for switch block design may be required.
In particular, such new switch block design could be focused on the so called T-switch, i.e. blocks connecting three lines or wires, as described for instance by A. Lodi et al. in the article entitled: “Compact Buffered Routing Architecture”, Lecture Notes in Computer Science, Field-Programmable Logic and Applications, pp. 179-188, Antwerp, Belgium, September 2004, which is incorporated by reference.
A standard implementation of such a T-switch is shown in FIG. 2A, globally indicated by 25 and comprises three T-switch buffers, as shown in FIG. 2B, globally indicated by 20.
The switch buffer 20 realizes the connection between a first line L0, a second line L1 or a third line L2. In particular, in FIG. 2B a T-switch buffer 20 having the lines L1 and L2 as input lines and the line L0 as output line. The T-switch 25 of FIG. 2A comprises two further T-switch buffers according to the following connection scheme:                input: L0 and L1; output L2; and        input: L0 and L2; output L1.        
In other words, the T-switch 25 comprises three T-switch buffers 20, as the one shown in FIG. 2B.
To do this, the switch buffer 20 comprises:    a first pass-transistor N0 connected between the first line L0 and a first internal node net0;    a second pass-transistor N1 connected between the second line L1 and a second internal node net1; and    a third pass-transistor N2 connected between the third line L2 and the second internal node net1.
In the example shown in the FIG. 2B, the pass-transistors N0-N2 are of the NMOS type.
The switch buffer 20 also includes a first inverter 21 and a second inverter 22, inserted between a first and a second voltage reference, in particular a supply voltage reference VDD and ground GND.
In particular, the first inverter 21 comprises a PMOS transistor P3 and an NMOS transistor N3 connected, in series to each other, between the supply voltage reference VDD and ground GND and having their gate terminals connected to each other and to a third internal node net2 and the common drain terminals connected to the first internal node net0.
In a same manner, the second inverter 22 has a PMOS transistor P4 and an NMOS transistor N4 connected, in series to each other, between the supply voltage reference VDD and ground GND and having their gate terminals connected to each other and to the second internal node net1 and the common drain terminals connected to the third internal node net2.
Finally, the switch buffer 20 includes a first P1 and a second pull up transistor P2 inserted between the supply voltage reference VDD and the second internal node net1, the second pull up transistor P2 having its gate terminal connected to the third internal node net2.
In particular, the pull up transistors P1 and P2 are high-voltage or Vth transistors (as indicated by a thicker gate line in the figure) of the PMOS type, all other transistors being standard transistors.
In particular, the T-switch buffer 20 has been designed using standard threshold transistors in its signal path in order to minimize the signal delay propagation, high threshold transistors (P1, P2) having been used for non-critical paths only.
In the case of a PiCoGA routing architecture, as shown in FIG. 2A, three T-switch buffer 20 are needed to implement a complete switch 25 with full connectivity.
Advantageously, the switch 25 realized by using such T-switch buffers 20 has a high speed. However, it shows a significant standby leakage current and thus a quite high static power consumption, which prevent its use in some applications, in particular when applied to programmable routing interconnections of FPGA architectures. In particular, its leakage currents are quite large when the switch 25 is off, i.e. in the idle state.